The present invention generally relates to a semiconductor device and, more particularly, to a semiconductor junction-field-effect-transistor (JFET) device with a predetermined pinch-off voltage and a method of fabricating the same.
In a semiconductor JFET device, by controlling the voltages applied to its gate and drain terminals, depletion regions and currents may be induced. Taking an n-channel JFET as an example, in operation, a negative voltage VGS and a positive voltage VDS may be applied to the gate terminals and the drain terminal, respectively. As the negative voltage VGS goes lower and reaches a threshold level (termed as “pinch-off voltage, VP”), the depletion regions may overlap each other in the channel region, resulting in a turn-off state of the JFET device. The pinch-off voltage VP may depend on the depth of the well region. However, it is difficult to precisely determine the depth of the well-region and in turn a desired pinch-off voltage VP during the fabricating process, as will be discussed below.
FIG. 1A is a schematic cross-sectional view of a JFET device 1-1 in prior art. Referring to FIG. 1A, when the gate terminals G1, G2 and the drain terminal D are biased at a negative voltage VGS and a positive voltage VDS respectively, depletion regions may be induced around the junctions between each P-well region and the N-type substrate, occupying portions of the channel region where an induced drain-to-source current IDS may flow. As the negative voltage VGS gets lower and reaches a pinch-off level, the channel region may be pinched by the depletion regions. Consequently, the drain-to-source current IDS may be largely reduced or switched off and the JFET device 1-1 may thus be turned off.
FIG. 1B is a schematic cross-sectional view illustrating a vertical-type JFET device 1-2 in prior art, wherein the drain region and the drain terminal are formed under the substrate. Referring to FIG. 1B, for such type of JFET device 1-2, the drain region is required to be precisely aligned with the source region formed on the substrate, which may need a complicated fabricating process. To address the issue, a lateral-type JFET device 1-3 has been developed.
FIG. 1C is a schematic cross-sectional view illustrating a lateral-type JFET device 1-3 in prior art. Referring to FIG. 1C, the source terminal S, the first, gate terminals G1, G2, and drain terminals D1, D2 are formed on the substrate. A depletion region may be induced around each of the junctions between the N-well region and the two P-well regions under the first and the second gate terminals G1, G2. When these terminals are appropriately biased, a first and a second current I1 and I2 may be induced, flowing in the N-well region, from drain terminals D1 and D2 to the source terminal S, respectively. The pinch-off voltage of the JFET device 1-3 may vary as the depth H0 of the N-well region varies. Moreover, the depth of the N-well region may be susceptible to fabrication process. As a result, it may be difficult to design a JFET device with a desirable pinch-off voltage.
It may therefore be desirable to have a JFET device with a predetermined pinch-off voltage VP. It may also be desirable to have a method of manufacturing such a JFET device.